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Silicon Epitaxial Reactor for Minimal Fab, Epitaxy, Miao Zhong, IntechOpen, DOI: 10.5772/intechopen.69986. It is due to the heat transport by the gas flow [9]. A unique feature of the Epsilon is the patented Bernoulli wand for non-contact wafer transfer. Three silicon carbide plates are stacked beneath the silicon wafer. Then, the reflector becomes high temperature. How? In addition, the environment inside the growth chamber is easily maintained and therefore the regular chamber cleaning for ordinary CVD reactors becomes less necessary for Minimal Fab. Figure 19(c) shows that the local non-uniformity of the wafer temperature remaining even using the wafer rotation is reduced by the high heat transport through the silicon carbide susceptor. Dotted lines: heat transport by radiation; solid lines: heat transport by conduction and gas flow. In Step A, the wafer holder temperature reaches 650°C. The thin plates are recognized to be the suitable reflector material. The epitaxial growth rate in Figure 18 is governed by the rate of surface chemical reaction [13]. A huge number of the device chips are produced in this manufacturing system. Process of silicon epitaxial growth by (a) Steps A–C and by (b) Steps A and B. The epitaxial growth rate is near 0.5 μm/min, which corresponds to the wafer temperature of 950°C following Eq. Next, it reacts with hydrogen to form silicon. The wafer temperature is influenced by many parameters [9] of lamp voltage, total gas flow rate and trichlorosilane gas concentration. The wafer rotation and the heat-conductive susceptor help to fabricate uniform silicon epitaxial films. Additionally, the cooling rate of the wafer becomes high. The gas flow containing the precursor gas from the gas nozzle takes the heat away from the wafer, QFlow. The epitaxial film thickness shows a hill and a valley along the x- and y-axes. The distance between the silicon wafer and the gas nozzle can be changed by finely adjusting QFlow. The half-inch silicon wafer is heated to 800–1100°C. The half-inch wafer temperature in a steady state is influenced by various conditions, such as the lamp voltage, V (V), the total gas flow rate, FTotalGas (sccm) and the trichlorosilane gas concentration, CTCS (%). In addition to the heating system, the highly reactive gas of chlorine trifluoride (ClF3) [8] is chosen for the reactor cleaning because it can easily remove the silicon film, unnecessarily formed in the CVD reactor, at various temperatures even at room temperature. However, it may result in slow heat conduction through it. By employing this geometry, QEm is high, because the emission of radiation heat is not disturbed. By concentrating the infrared flux, QIR effectively reaches and locally heats the substrate with minimizing the heat loss. The typical silicon CVD process [14] utilizes hydrogen chloride gas near 1200°C. The inner zone and the outer zone gas inlets have diameters of 7 and 24 mm, respectively. In Section 4, the heat transport near the wafer is evaluated [12]. Cooling rate of half-inch silicon wafer in the minimal CVD reactor and the reactor using the ordinary type reflector. Overall, important parameters are listed in Table 2. Figure 8 shows the wafer holder temperature during the silicon deposition. We share our knowledge and peer-reveiwed research papers with libraries, scientific and engineering societies, and also work with corporate R&D departments and government entities. The concentrated infrared flux effectively heats the small substrate; the thermal process becomes very rapid. Particularly, the massive metallic parts require long time for reaching a thermal steady state. Heat transport from halogen lamp to silicon wafer through (a) Type-I and (b) Type-II reflectors. In addition, the environment inside the growth chamber is easily maintained and therefore the regular … Cost-effective and mass production of size-controlled wafers becomes one of the future trends for electronic devices. Wafer temperature changing with the lamp voltage and the total gas flow rate. Contact our London head office or media team here. The parallel process of Steps A and B is expected to become quicker. Figure 9 shows the relationship between the wafer temperature, the film surface and the quartz wall deposition. The CVD reactor for the large-diameter wafer has the large infrared lamp module consisting of large and thick reflector plates [9, 10, 11]. When the trichlorosilane gas is added from 9 to 13 min, the wafer holder temperature increases, as shown using white squares, and reaches 609°C. Next, the wafer temperature is adjusted to 700–1000°C for Step B, forming the silicon epitaxial film for several minutes by the chemical reaction [13] following Eq. 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